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typo
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@ -184,14 +184,14 @@ bool haveOSXSAVE() noexcept
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return (CpuInfo(0x1).registers.ecx >> 27) & 1u;
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return (CpuInfo(0x1).registers.ecx >> 27) & 1u;
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}
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}
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inline bool haveSIMDExtention(UInt32 code) noexcept
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inline bool haveSIMDExtension(UInt32 code) noexcept
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{
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{
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#if defined(__x86_64__) || defined(__i386__)
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#if defined(__x86_64__) || defined(__i386__)
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// http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf
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// http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf
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// https://bugs.chromium.org/p/chromium/issues/detail?id=375968
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// https://bugs.chromium.org/p/chromium/issues/detail?id=375968
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return haveOSXSAVE() // implies haveXSAVE()
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return haveOSXSAVE() // implies haveXSAVE()
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&& (our_xgetbv(0) & 6u) == 6u // XMM state and YMM state are enabled by OS
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&& (our_xgetbv(0) & 6u) == 6u // XMM state and YMM state are enabled by OS
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&& ((CpuInfo(0x1).registers.ecx >> code) & 1u); // Extention bit
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&& ((CpuInfo(0x1).registers.ecx >> code) & 1u); // Extension bit
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#else
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#else
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return false;
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return false;
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#endif
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#endif
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@ -199,7 +199,7 @@ inline bool haveSIMDExtention(UInt32 code) noexcept
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bool haveAVX() noexcept
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bool haveAVX() noexcept
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{
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{
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return haveSIMDExtention(28); // AVX bit
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return haveSIMDExtension(28); // AVX bit
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}
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}
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bool haveFMA() noexcept
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bool haveFMA() noexcept
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@ -323,17 +323,17 @@ bool haveRDRAND() noexcept
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bool haveAMXBF16() noexcept
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bool haveAMXBF16() noexcept
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{
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{
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return haveSIMDExtention(22); // AMX-BF16 bit
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return haveSIMDExtension(22); // AMX-BF16 bit
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}
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}
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bool haveAMXTILE() noexcept
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bool haveAMXTILE() noexcept
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{
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{
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return haveSIMDExtention(24); // AMX-TILE bit
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return haveSIMDExtension(24); // AMX-TILE bit
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}
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}
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bool haveAMXINT8() noexcept
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bool haveAMXINT8() noexcept
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{
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{
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return haveSIMDExtention(25); // AMX-INT8 bit
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return haveSIMDExtension(25); // AMX-INT8 bit
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}
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}
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struct CpuFlagsCache
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struct CpuFlagsCache
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