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Renamed events
This commit is contained in:
Andrey Skobtsov
parent
182e4f2c0b
commit
e7bea6e03a
@ -178,48 +178,48 @@
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M(OSReadChars, "Number of bytes read from filesystem, including page cache.") \
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M(OSWriteChars, "Number of bytes written to filesystem, including page cache.") \
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\
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M(PERF_COUNT_HW_CPU_CYCLES, "Total cycles. Be wary of what happens during CPU frequency scaling.") \
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M(PERF_COUNT_HW_CPU_CYCLES_RUNNING, "Total cycles (<time running>).") \
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M(PERF_COUNT_HW_CPU_CYCLES_ENABLED, "Total cycles (<time enabled>).") \
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M(PERF_COUNT_HW_INSTRUCTIONS, "Retired instructions. Be careful, these can be affected by various issues, most notably hardware interrupt counts.") \
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M(PERF_COUNT_HW_INSTRUCTIONS_RUNNING, "Retired instructions (<time running>).") \
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M(PERF_COUNT_HW_INSTRUCTIONS_ENABLED, "Retired instructions (<time enabled> * 100%).") \
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M(PERF_COUNT_HW_CACHE_REFERENCES, "Cache accesses. Usually this indicates Last Level Cache accesses but this may vary depending on your CPU. This may include prefetches and coherency messages; again this depends on the design of your CPU.") \
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M(PERF_COUNT_HW_CACHE_REFERENCES_RUNNING, "Cache accesses (<time running>).") \
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M(PERF_COUNT_HW_CACHE_REFERENCES_ENABLED, "Cache accesses (<time enabled>).") \
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M(PERF_COUNT_HW_CACHE_MISSES, "Cache misses. Usually this indicates Last Level Cache misses; this is intended to be used in con‐junction with the PERF_COUNT_HW_CACHE_REFERENCES event to calculate cache miss rates.") \
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M(PERF_COUNT_HW_CACHE_MISSES_RUNNING, "Cache misses (<time running> / <time enabled> * 100%).") \
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M(PERF_COUNT_HW_CACHE_MISSES_ENABLED, "Cache misses (<time enabled>).") \
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M(PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "Retired branch instructions. Prior to Linux 2.6.35, this used the wrong event on AMD processors.") \
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M(PERF_COUNT_HW_BRANCH_INSTRUCTIONS_RUNNING, "Retired branch instructions (<time running>).") \
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M(PERF_COUNT_HW_BRANCH_INSTRUCTIONS_ENABLED, "Retired branch instructions (<time enabled>).") \
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M(PERF_COUNT_HW_BRANCH_MISSES, "Mispredicted branch instructions.") \
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M(PERF_COUNT_HW_BRANCH_MISSES_RUNNING, "Mispredicted branch instructions (<time running>).") \
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M(PERF_COUNT_HW_BRANCH_MISSES_ENABLED, "Mispredicted branch instructions (<time enabled>).") \
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M(PERF_COUNT_HW_BUS_CYCLES, "Bus cycles, which can be different from total cycles.") \
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M(PERF_COUNT_HW_BUS_CYCLES_RUNNING, "Bus cycles, which can be different from total cycles (<time running>).") \
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M(PERF_COUNT_HW_BUS_CYCLES_ENABLED, "Bus cycles, which can be different from total cycles (<time enabled>).") \
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M(PERF_COUNT_HW_STALLED_CYCLES_FRONTEND, "Stalled cycles during issue.") \
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M(PERF_COUNT_HW_STALLED_CYCLES_FRONTEND_RUNNING, "Stalled cycles during issue (<time running>).") \
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M(PERF_COUNT_HW_STALLED_CYCLES_FRONTEND_ENABLED, "Stalled cycles during issue (<time enabled>).") \
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M(PERF_COUNT_HW_STALLED_CYCLES_BACKEND, "Stalled cycles during retirement.") \
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M(PERF_COUNT_HW_STALLED_CYCLES_BACKEND_RUNNING, "Stalled cycles during retirement (<time running>).") \
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M(PERF_COUNT_HW_STALLED_CYCLES_BACKEND_ENABLED, "Stalled cycles during retirement (<time enabled>).") \
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M(PERF_COUNT_HW_REF_CPU_CYCLES, "Total cycles; not affected by CPU frequency scaling.") \
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M(PERF_COUNT_HW_REF_CPU_CYCLES_RUNNING, "Total cycles; not affected by CPU frequency scaling (<time running>).") \
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M(PERF_COUNT_HW_REF_CPU_CYCLES_ENABLED, "Total cycles; not affected by CPU frequency scaling (<time enabled>).") \
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M(PerfCpuCycles, "Total cycles. Be wary of what happens during CPU frequency scaling.") \
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M(PerfCpuCyclesRunning, "Total cycles (<time running>).") \
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M(PerfCpuCyclesEnabled, "Total cycles (<time enabled>).") \
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M(PerfInstructions, "Retired instructions. Be careful, these can be affected by various issues, most notably hardware interrupt counts.") \
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M(PerfInstructionsRunning, "Retired instructions (<time running>).") \
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M(PerfInstructionsEnabled, "Retired instructions (<time enabled>).") \
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M(PerfCacheReferences, "Cache accesses. Usually this indicates Last Level Cache accesses but this may vary depending on your CPU. This may include prefetches and coherency messages; again this depends on the design of your CPU.") \
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M(PerfCacheReferencesRunning, "Cache accesses (<time running>).") \
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M(PerfCacheReferencesEnabled, "Cache accesses (<time enabled>).") \
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M(PerfCacheMisses, "Cache misses. Usually this indicates Last Level Cache misses; this is intended to be used in con‐junction with the PERFCOUNTHWCACHEREFERENCES event to calculate cache miss rates.") \
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M(PerfCacheMissesRunning, "Cache misses (<time running>).") \
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M(PerfCacheMissesEnabled, "Cache misses (<time enabled>).") \
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M(PerfBranchInstructions, "Retired branch instructions. Prior to Linux 2.6.35, this used the wrong event on AMD processors.") \
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M(PerfBranchInstructionsRunning, "Retired branch instructions (<time running>).") \
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M(PerfBranchInstructionsEnabled, "Retired branch instructions (<time enabled>).") \
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M(PerfBranchMisses, "Mispredicted branch instructions.") \
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M(PerfBranchMissesRunning, "Mispredicted branch instructions (<time running>).") \
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M(PerfBranchMissesEnabled, "Mispredicted branch instructions (<time enabled>).") \
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M(PerfBusCycles, "Bus cycles, which can be different from total cycles.") \
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M(PerfBusCyclesRunning, "Bus cycles, which can be different from total cycles (<time running>).") \
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M(PerfBusCyclesEnabled, "Bus cycles, which can be different from total cycles (<time enabled>).") \
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M(PerfStalledCyclesFrontend, "Stalled cycles during issue.") \
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M(PerfStalledCyclesFrontendRunning, "Stalled cycles during issue (<time running>).") \
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M(PerfStalledCyclesFrontendEnabled, "Stalled cycles during issue (<time enabled>).") \
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M(PerfStalledCyclesBackend, "Stalled cycles during retirement.") \
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M(PerfStalledCyclesBackendRunning, "Stalled cycles during retirement (<time running>).") \
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M(PerfStalledCyclesBackendEnabled, "Stalled cycles during retirement (<time enabled>).") \
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M(PerfRefCpuCycles, "Total cycles; not affected by CPU frequency scaling.") \
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M(PerfRefCpuCyclesRunning, "Total cycles; not affected by CPU frequency scaling (<time running>).") \
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M(PerfRefCpuCyclesEnabled, "Total cycles; not affected by CPU frequency scaling (<time enabled>).") \
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\
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M(PERF_COUNT_SW_TASK_CLOCK, "A clock count specific to the task that is running") \
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M(PERF_COUNT_SW_PAGE_FAULTS, "Number of page faults") \
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M(PERF_COUNT_SW_CONTEXT_SWITCHES, "Number of context switches") \
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M(PERF_COUNT_SW_CPU_MIGRATIONS, "Number of times the process has migrated to a new CPU") \
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M(PERF_COUNT_SW_PAGE_FAULTS_MIN, "Number of minor page faults. These did not require disk I/O to handle") \
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M(PERF_COUNT_SW_PAGE_FAULTS_MAJ, "Number of major page faults. These required disk I/O to handle") \
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M(PERF_COUNT_SW_ALIGNMENT_FAULTS, "Number of alignment faults. These happen when unaligned memory accesses happen; the kernel can handle these but it reduces performance. This happens only on some architectures (never on x86).") \
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M(PERF_COUNT_SW_EMULATION_FAULTS, "Number of emulation faults. The kernel sometimes traps on unimplemented instructions and emulates them for user space. This can negatively impact performance.") \
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M(PerfTaskClock, "A clock count specific to the task that is running") \
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M(PerfPageFaults, "Number of page faults") \
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M(PerfContextSwitches, "Number of context switches") \
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M(PerfCpuMigrations, "Number of times the process has migrated to a new CPU") \
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M(PerfPageFaultsMin, "Number of minor page faults. These did not require disk I/O to handle") \
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M(PerfPageFaultsMaj, "Number of major page faults. These required disk I/O to handle") \
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M(PerfAlignmentFaults, "Number of alignment faults. These happen when unaligned memory accesses happen; the kernel can handle these but it reduces performance. This happens only on some architectures (never on x86).") \
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M(PerfEmulationFaults, "Number of emulation faults. The kernel sometimes traps on unimplemented instructions and emulates them for user space. This can negatively impact performance.") \
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\
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M(PERF_CUSTOM_INSTRUCTIONS_PER_CPU_CYCLE_SCALED, "") \
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M(PERF_CUSTOM_INSTRUCTIONS_PER_CPU_CYCLE, "") \
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M(PerfCustomInstructionsPerCpuCycleScaled, "") \
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M(PerfCustomInstructionsPerCpuCycle, "") \
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\
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M(CreatedHTTPConnections, "Total amount of created HTTP connections (closed or opened).") \
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\
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@ -123,50 +123,46 @@ static PerfEventInfo softwareEvent(int event_config, ProfileEvents::Event profil
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};
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}
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static PerfEventInfo hardwareEvent(int event_config, ProfileEvents::Event profile_event, std::optional<ProfileEvents::Event> pe_running, std::optional<ProfileEvents::Event> pe_enabled)
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{
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return PerfEventInfo
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{
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.event_type = perf_type_id::PERF_TYPE_HARDWARE,
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.event_config = event_config,
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.profile_event = profile_event,
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.profile_event_running = pe_running,
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.profile_event_enabled = pe_enabled
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};
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}
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#define HARDWARE_WITH_TIME(EVENT_NAME) \
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hardwareEvent(EVENT_NAME, ProfileEvents::EVENT_NAME, {ProfileEvents::EVENT_NAME##_RUNNING}, {ProfileEvents::EVENT_NAME##_ENABLED})
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#define HARDWARE_EVENT(PERF_NAME, LOCAL_NAME) \
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PerfEventInfo \
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{ \
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.event_type = perf_type_id::PERF_TYPE_HARDWARE, \
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.event_config = PERF_NAME, \
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.profile_event = ProfileEvents::LOCAL_NAME, \
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.profile_event_running = {ProfileEvents::LOCAL_NAME##Running}, \
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.profile_event_enabled = {ProfileEvents::LOCAL_NAME##Enabled} \
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}
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// descriptions' source: http://man7.org/linux/man-pages/man2/perf_event_open.2.html
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const PerfEventInfo PerfEventsCounters::raw_events_info[] = {
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HARDWARE_WITH_TIME(PERF_COUNT_HW_CPU_CYCLES),
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HARDWARE_WITH_TIME(PERF_COUNT_HW_INSTRUCTIONS),
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HARDWARE_WITH_TIME(PERF_COUNT_HW_CACHE_REFERENCES),
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HARDWARE_WITH_TIME(PERF_COUNT_HW_CACHE_MISSES),
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HARDWARE_WITH_TIME(PERF_COUNT_HW_BRANCH_INSTRUCTIONS),
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HARDWARE_WITH_TIME(PERF_COUNT_HW_BRANCH_MISSES),
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HARDWARE_WITH_TIME(PERF_COUNT_HW_BUS_CYCLES),
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HARDWARE_WITH_TIME(PERF_COUNT_HW_STALLED_CYCLES_FRONTEND),
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HARDWARE_WITH_TIME(PERF_COUNT_HW_STALLED_CYCLES_BACKEND),
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HARDWARE_WITH_TIME(PERF_COUNT_HW_REF_CPU_CYCLES),
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HARDWARE_EVENT(PERF_COUNT_HW_CPU_CYCLES, PerfCpuCycles),
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HARDWARE_EVENT(PERF_COUNT_HW_INSTRUCTIONS, PerfInstructions),
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HARDWARE_EVENT(PERF_COUNT_HW_CACHE_REFERENCES, PerfCacheReferences),
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HARDWARE_EVENT(PERF_COUNT_HW_CACHE_MISSES, PerfCacheMisses),
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HARDWARE_EVENT(PERF_COUNT_HW_BRANCH_INSTRUCTIONS, PerfBranchInstructions),
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HARDWARE_EVENT(PERF_COUNT_HW_BRANCH_MISSES, PerfBranchMisses),
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HARDWARE_EVENT(PERF_COUNT_HW_BUS_CYCLES, PerfBusCycles),
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HARDWARE_EVENT(PERF_COUNT_HW_STALLED_CYCLES_FRONTEND, PerfStalledCyclesFrontend),
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HARDWARE_EVENT(PERF_COUNT_HW_STALLED_CYCLES_BACKEND, PerfStalledCyclesBackend),
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HARDWARE_EVENT(PERF_COUNT_HW_REF_CPU_CYCLES, PerfRefCpuCycles),
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// This reports the CPU clock, a high-resolution per-CPU timer.
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// a bit broken according to this: https://stackoverflow.com/a/56967896
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// softwareEvent(PERF_COUNT_SW_CPU_CLOCK, ProfileEvents::PERF_COUNT_SW_CPU_CLOCK),
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softwareEvent(PERF_COUNT_SW_TASK_CLOCK, ProfileEvents::PERF_COUNT_SW_TASK_CLOCK),
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softwareEvent(PERF_COUNT_SW_PAGE_FAULTS, ProfileEvents::PERF_COUNT_SW_PAGE_FAULTS),
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softwareEvent(PERF_COUNT_SW_CONTEXT_SWITCHES, ProfileEvents::PERF_COUNT_SW_CONTEXT_SWITCHES),
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softwareEvent(PERF_COUNT_SW_CPU_MIGRATIONS, ProfileEvents::PERF_COUNT_SW_CPU_MIGRATIONS),
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softwareEvent(PERF_COUNT_SW_PAGE_FAULTS_MIN, ProfileEvents::PERF_COUNT_SW_PAGE_FAULTS_MIN),
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softwareEvent(PERF_COUNT_SW_PAGE_FAULTS_MAJ, ProfileEvents::PERF_COUNT_SW_PAGE_FAULTS_MAJ),
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softwareEvent(PERF_COUNT_SW_ALIGNMENT_FAULTS, ProfileEvents::PERF_COUNT_SW_ALIGNMENT_FAULTS),
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softwareEvent(PERF_COUNT_SW_EMULATION_FAULTS, ProfileEvents::PERF_COUNT_SW_EMULATION_FAULTS)
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// softwareEvent(PERF_COUNT_SW_CPU_CLOCK, ProfileEvents::PerfCpuClock),
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softwareEvent(PERF_COUNT_SW_TASK_CLOCK, ProfileEvents::PerfTaskClock),
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softwareEvent(PERF_COUNT_SW_PAGE_FAULTS, ProfileEvents::PerfPageFaults),
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softwareEvent(PERF_COUNT_SW_CONTEXT_SWITCHES, ProfileEvents::PerfContextSwitches),
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softwareEvent(PERF_COUNT_SW_CPU_MIGRATIONS, ProfileEvents::PerfCpuMigrations),
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softwareEvent(PERF_COUNT_SW_PAGE_FAULTS_MIN, ProfileEvents::PerfPageFaultsMin),
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softwareEvent(PERF_COUNT_SW_PAGE_FAULTS_MAJ, ProfileEvents::PerfPageFaultsMaj),
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softwareEvent(PERF_COUNT_SW_ALIGNMENT_FAULTS, ProfileEvents::PerfAlignmentFaults),
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softwareEvent(PERF_COUNT_SW_EMULATION_FAULTS, ProfileEvents::PerfEmulationFaults)
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// This is a placeholder event that counts nothing. Informational sample record types such as mmap or
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// comm must be associated with an active event. This dummy event allows gathering such records
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// without requiring a counting event.
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// softwareEventInfo(PERF_COUNT_SW_DUMMY, ProfileEvents::PERF_COUNT_SW_DUMMY)
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};
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#undef HARDWARE_WITH_TIME
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#undef HARDWARE_EVENT
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thread_local PerfDescriptorsHolder PerfEventsCounters::thread_events_descriptors_holder{};
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thread_local bool PerfEventsCounters::thread_events_descriptors_opened = false;
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@ -363,8 +359,8 @@ void PerfEventsCounters::finalizeProfileEvents(PerfEventsCounters & counters, Pr
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? counters.getRawValue(PERF_TYPE_HARDWARE, PERF_COUNT_HW_INSTRUCTIONS).value / hw_ref_cpu_cycles
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: 0;
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profile_events.increment(ProfileEvents::PERF_CUSTOM_INSTRUCTIONS_PER_CPU_CYCLE_SCALED, instructions_per_cpu_scaled);
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profile_events.increment(ProfileEvents::PERF_CUSTOM_INSTRUCTIONS_PER_CPU_CYCLE, instructions_per_cpu);
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profile_events.increment(ProfileEvents::PerfCustomInstructionsPerCpuCycleScaled, instructions_per_cpu_scaled);
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profile_events.increment(ProfileEvents::PerfCustomInstructionsPerCpuCycle, instructions_per_cpu);
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current_thread_counters = nullptr;
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}
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@ -36,49 +36,49 @@ namespace ProfileEvents
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extern const Event OSReadBytes;
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extern const Event OSWriteBytes;
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extern const Event PERF_COUNT_HW_CPU_CYCLES;
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extern const Event PERF_COUNT_HW_CPU_CYCLES_RUNNING;
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extern const Event PERF_COUNT_HW_CPU_CYCLES_ENABLED;
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extern const Event PERF_COUNT_HW_INSTRUCTIONS;
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extern const Event PERF_COUNT_HW_INSTRUCTIONS_RUNNING;
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extern const Event PERF_COUNT_HW_INSTRUCTIONS_ENABLED;
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extern const Event PERF_COUNT_HW_CACHE_REFERENCES;
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extern const Event PERF_COUNT_HW_CACHE_REFERENCES_RUNNING;
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extern const Event PERF_COUNT_HW_CACHE_REFERENCES_ENABLED;
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extern const Event PERF_COUNT_HW_CACHE_MISSES;
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extern const Event PERF_COUNT_HW_CACHE_MISSES_RUNNING;
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extern const Event PERF_COUNT_HW_CACHE_MISSES_ENABLED;
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extern const Event PERF_COUNT_HW_BRANCH_INSTRUCTIONS;
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extern const Event PERF_COUNT_HW_BRANCH_INSTRUCTIONS_RUNNING;
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extern const Event PERF_COUNT_HW_BRANCH_INSTRUCTIONS_ENABLED;
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extern const Event PERF_COUNT_HW_BRANCH_MISSES;
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extern const Event PERF_COUNT_HW_BRANCH_MISSES_RUNNING;
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extern const Event PERF_COUNT_HW_BRANCH_MISSES_ENABLED;
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extern const Event PERF_COUNT_HW_BUS_CYCLES;
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extern const Event PERF_COUNT_HW_BUS_CYCLES_RUNNING;
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extern const Event PERF_COUNT_HW_BUS_CYCLES_ENABLED;
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extern const Event PERF_COUNT_HW_STALLED_CYCLES_FRONTEND;
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extern const Event PERF_COUNT_HW_STALLED_CYCLES_FRONTEND_RUNNING;
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extern const Event PERF_COUNT_HW_STALLED_CYCLES_FRONTEND_ENABLED;
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extern const Event PERF_COUNT_HW_STALLED_CYCLES_BACKEND;
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extern const Event PERF_COUNT_HW_STALLED_CYCLES_BACKEND_RUNNING;
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extern const Event PERF_COUNT_HW_STALLED_CYCLES_BACKEND_ENABLED;
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extern const Event PERF_COUNT_HW_REF_CPU_CYCLES;
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extern const Event PERF_COUNT_HW_REF_CPU_CYCLES_RUNNING;
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extern const Event PERF_COUNT_HW_REF_CPU_CYCLES_ENABLED;
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extern const Event PerfCpuCycles;
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extern const Event PerfCpuCyclesRunning;
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extern const Event PerfCpuCyclesEnabled;
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extern const Event PerfInstructions;
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extern const Event PerfInstructionsRunning;
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extern const Event PerfInstructionsEnabled;
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extern const Event PerfCacheReferences;
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extern const Event PerfCacheReferencesRunning;
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extern const Event PerfCacheReferencesEnabled;
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extern const Event PerfCacheMisses;
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extern const Event PerfCacheMissesRunning;
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extern const Event PerfCacheMissesEnabled;
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extern const Event PerfBranchInstructions;
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extern const Event PerfBranchInstructionsRunning;
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extern const Event PerfBranchInstructionsEnabled;
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extern const Event PerfBranchMisses;
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extern const Event PerfBranchMissesRunning;
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extern const Event PerfBranchMissesEnabled;
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extern const Event PerfBusCycles;
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extern const Event PerfBusCyclesRunning;
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extern const Event PerfBusCyclesEnabled;
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extern const Event PerfStalledCyclesFrontend;
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extern const Event PerfStalledCyclesFrontendRunning;
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extern const Event PerfStalledCyclesFrontendEnabled;
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extern const Event PerfStalledCyclesBackend;
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extern const Event PerfStalledCyclesBackendRunning;
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extern const Event PerfStalledCyclesBackendEnabled;
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extern const Event PerfRefCpuCycles;
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extern const Event PerfRefCpuCyclesRunning;
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extern const Event PerfRefCpuCyclesEnabled;
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// extern const Event PERF_COUNT_SW_CPU_CLOCK;
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extern const Event PERF_COUNT_SW_TASK_CLOCK;
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extern const Event PERF_COUNT_SW_PAGE_FAULTS;
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extern const Event PERF_COUNT_SW_CONTEXT_SWITCHES;
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extern const Event PERF_COUNT_SW_CPU_MIGRATIONS;
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extern const Event PERF_COUNT_SW_PAGE_FAULTS_MIN;
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extern const Event PERF_COUNT_SW_PAGE_FAULTS_MAJ;
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extern const Event PERF_COUNT_SW_ALIGNMENT_FAULTS;
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extern const Event PERF_COUNT_SW_EMULATION_FAULTS;
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// extern const Event PerfCpuClock;
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extern const Event PerfTaskClock;
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extern const Event PerfPageFaults;
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extern const Event PerfContextSwitches;
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extern const Event PerfCpuMigrations;
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extern const Event PerfPageFaultsMin;
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extern const Event PerfPageFaultsMaj;
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extern const Event PerfAlignmentFaults;
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extern const Event PerfEmulationFaults;
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extern const Event PERF_CUSTOM_INSTRUCTIONS_PER_CPU_CYCLE_SCALED;
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extern const Event PERF_CUSTOM_INSTRUCTIONS_PER_CPU_CYCLE;
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extern const Event PerfCustomInstructionsPerCpuCycleScaled;
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extern const Event PerfCustomInstructionsPerCpuCycle;
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#endif
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}
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