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138 lines
3.7 KiB
C++
138 lines
3.7 KiB
C++
// Copyright 2006-2008 The RE2 Authors. All Rights Reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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#ifndef RE2_UTIL_ATOMICOPS_H__
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#define RE2_UTIL_ATOMICOPS_H__
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// The memory ordering constraints resemble the ones in C11.
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// RELAXED - no memory ordering, just an atomic operation.
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// CONSUME - data-dependent ordering.
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// ACQUIRE - prevents memory accesses from hoisting above the operation.
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// RELEASE - prevents memory accesses from sinking below the operation.
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#if (__clang_major__ * 100 + __clang_minor__ >= 303) || \
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(__GNUC__ * 1000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__ >= 40801)
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#define ATOMIC_LOAD_RELAXED(x, p) do { (x) = __atomic_load_n((p), __ATOMIC_RELAXED); } while (0)
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#define ATOMIC_LOAD_CONSUME(x, p) do { (x) = __atomic_load_n((p), __ATOMIC_CONSUME); } while (0)
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#define ATOMIC_LOAD_ACQUIRE(x, p) do { (x) = __atomic_load_n((p), __ATOMIC_ACQUIRE); } while (0)
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#define ATOMIC_STORE_RELAXED(p, v) __atomic_store_n((p), (v), __ATOMIC_RELAXED)
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#define ATOMIC_STORE_RELEASE(p, v) __atomic_store_n((p), (v), __ATOMIC_RELEASE)
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#else // old compiler
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#define ATOMIC_LOAD_RELAXED(x, p) do { (x) = *(p); } while (0)
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#define ATOMIC_LOAD_CONSUME(x, p) do { (x) = *(p); MaybeReadMemoryBarrier(); } while (0)
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#define ATOMIC_LOAD_ACQUIRE(x, p) do { (x) = *(p); ReadMemoryBarrier(); } while (0)
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#define ATOMIC_STORE_RELAXED(p, v) do { *(p) = (v); } while (0)
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#define ATOMIC_STORE_RELEASE(p, v) do { WriteMemoryBarrier(); *(p) = (v); } while (0)
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// WriteMemoryBarrier(), ReadMemoryBarrier() and MaybeReadMemoryBarrier()
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// are an implementation detail and must not be used in the rest of the code.
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#if defined(__i386__)
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static inline void WriteMemoryBarrier() {
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int x;
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__asm__ __volatile__("xchgl (%0),%0" // The lock prefix is implicit for xchg.
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:: "r" (&x));
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}
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#elif defined(__x86_64__)
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// 64-bit implementations of memory barrier can be simpler, because
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// "sfence" is guaranteed to exist.
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static inline void WriteMemoryBarrier() {
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__asm__ __volatile__("sfence" : : : "memory");
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}
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#elif defined(__ppc__)
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static inline void WriteMemoryBarrier() {
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__asm__ __volatile__("eieio" : : : "memory");
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}
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#elif defined(__alpha__)
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static inline void WriteMemoryBarrier() {
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__asm__ __volatile__("wmb" : : : "memory");
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}
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#elif defined(__aarch64__)
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static inline void WriteMemoryBarrier() {
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__asm__ __volatile__("dmb st" : : : "memory");
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}
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#else
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#include "util/mutex.h"
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static inline void WriteMemoryBarrier() {
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// Slight overkill, but good enough:
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// any mutex implementation must have
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// a read barrier after the lock operation and
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// a write barrier before the unlock operation.
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//
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// It may be worthwhile to write architecture-specific
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// barriers for the common platforms, as above, but
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// this is a correct fallback.
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re2::Mutex mu;
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re2::MutexLock l(&mu);
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}
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/*
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#error Need WriteMemoryBarrier for architecture.
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// Windows
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inline void WriteMemoryBarrier() {
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LONG x;
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::InterlockedExchange(&x, 0);
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}
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*/
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#endif
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// Alpha has very weak memory ordering. If relying on WriteBarriers, one must
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// use read barriers for the readers too.
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#if defined(__alpha__)
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static inline void MaybeReadMemoryBarrier() {
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__asm__ __volatile__("mb" : : : "memory");
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}
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#else
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static inline void MaybeReadMemoryBarrier() {}
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#endif // __alpha__
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// Read barrier for various targets.
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#if defined(__aarch64__)
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static inline void ReadMemoryBarrier() {
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__asm__ __volatile__("dmb ld" : : : "memory");
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}
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#elif defined(__alpha__)
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static inline void ReadMemoryBarrier() {
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__asm__ __volatile__("mb" : : : "memory");
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}
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#else
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static inline void ReadMemoryBarrier() {}
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#endif
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#endif // old compiler
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#ifndef NO_THREAD_SAFETY_ANALYSIS
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#define NO_THREAD_SAFETY_ANALYSIS
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#endif
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#endif // RE2_UTIL_ATOMICOPS_H__
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