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154 lines
6.8 KiB
C++
154 lines
6.8 KiB
C++
/************************** instrset_detect.cpp ****************************
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| Author: Agner Fog
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| Date created: 2012-05-30
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| Last modified: 2014-07-23
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| Version: 1.14
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| Project: vector classes
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| Description:
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| Functions for checking which instruction sets are supported.
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| (c) Copyright 2012 - 2014 GNU General Public License http://www.gnu.org/licenses
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\*****************************************************************************/
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#include "instrset.h"
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// Define interface to cpuid instruction.
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// input: eax = functionnumber, ecx = 0
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// output: eax = output[0], ebx = output[1], ecx = output[2], edx = output[3]
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static inline void cpuid (int output[4], int functionnumber) {
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#if defined (_MSC_VER) || defined (__INTEL_COMPILER) // Microsoft or Intel compiler, intrin.h included
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__cpuidex(output, functionnumber, 0); // intrinsic function for CPUID
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#elif defined(__GNUC__) || defined(__clang__) // use inline assembly, Gnu/AT&T syntax
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int a, b, c, d;
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__asm("cpuid" : "=a"(a),"=b"(b),"=c"(c),"=d"(d) : "a"(functionnumber),"c"(0) : );
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output[0] = a;
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output[1] = b;
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output[2] = c;
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output[3] = d;
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#else // unknown platform. try inline assembly with masm/intel syntax
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__asm {
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mov eax, functionnumber
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xor ecx, ecx
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cpuid;
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mov esi, output
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mov [esi], eax
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mov [esi+4], ebx
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mov [esi+8], ecx
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mov [esi+12], edx
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}
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#endif
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}
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// Define interface to xgetbv instruction
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static inline int64_t xgetbv (int ctr) {
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#if (defined (_MSC_FULL_VER) && _MSC_FULL_VER >= 160040000) || (defined (__INTEL_COMPILER) && __INTEL_COMPILER >= 1200) // Microsoft or Intel compiler supporting _xgetbv intrinsic
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return _xgetbv(ctr); // intrinsic function for XGETBV
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#elif defined(__GNUC__) // use inline assembly, Gnu/AT&T syntax
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uint32_t a, d;
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__asm("xgetbv" : "=a"(a),"=d"(d) : "c"(ctr) : );
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return a | (uint64_t(d) << 32);
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#else // #elif defined (_WIN32) // other compiler. try inline assembly with masm/intel/MS syntax
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uint32_t a, d;
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__asm {
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mov ecx, ctr
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_emit 0x0f
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_emit 0x01
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_emit 0xd0 ; // xgetbv
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mov a, eax
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mov d, edx
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}
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return a | (uint64_t(d) << 32);
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#endif
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}
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/* find supported instruction set
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return value:
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0 = 80386 instruction set
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1 or above = SSE (XMM) supported by CPU (not testing for O.S. support)
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2 or above = SSE2
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3 or above = SSE3
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4 or above = Supplementary SSE3 (SSSE3)
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5 or above = SSE4.1
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6 or above = SSE4.2
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7 or above = AVX supported by CPU and operating system
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8 or above = AVX2
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9 or above = AVX512F
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*/
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int instrset_detect(void) {
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static int iset = -1; // remember value for next call
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if (iset >= 0) {
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return iset; // called before
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}
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iset = 0; // default value
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int abcd[4] = {0,0,0,0}; // cpuid results
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cpuid(abcd, 0); // call cpuid function 0
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if (abcd[0] == 0) return iset; // no further cpuid function supported
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cpuid(abcd, 1); // call cpuid function 1 for feature flags
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if ((abcd[3] & (1 << 0)) == 0) return iset; // no floating point
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if ((abcd[3] & (1 << 23)) == 0) return iset; // no MMX
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if ((abcd[3] & (1 << 15)) == 0) return iset; // no conditional move
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if ((abcd[3] & (1 << 24)) == 0) return iset; // no FXSAVE
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if ((abcd[3] & (1 << 25)) == 0) return iset; // no SSE
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iset = 1; // 1: SSE supported
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if ((abcd[3] & (1 << 26)) == 0) return iset; // no SSE2
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iset = 2; // 2: SSE2 supported
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if ((abcd[2] & (1 << 0)) == 0) return iset; // no SSE3
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iset = 3; // 3: SSE3 supported
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if ((abcd[2] & (1 << 9)) == 0) return iset; // no SSSE3
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iset = 4; // 4: SSSE3 supported
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if ((abcd[2] & (1 << 19)) == 0) return iset; // no SSE4.1
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iset = 5; // 5: SSE4.1 supported
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if ((abcd[2] & (1 << 23)) == 0) return iset; // no POPCNT
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if ((abcd[2] & (1 << 20)) == 0) return iset; // no SSE4.2
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iset = 6; // 6: SSE4.2 supported
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if ((abcd[2] & (1 << 27)) == 0) return iset; // no OSXSAVE
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if ((xgetbv(0) & 6) != 6) return iset; // AVX not enabled in O.S.
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if ((abcd[2] & (1 << 28)) == 0) return iset; // no AVX
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iset = 7; // 7: AVX supported
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cpuid(abcd, 7); // call cpuid leaf 7 for feature flags
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if ((abcd[1] & (1 << 5)) == 0) return iset; // no AVX2
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iset = 8; // 8: AVX2 supported
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cpuid(abcd, 0xD); // call cpuid leaf 0xD for feature flags
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if ((abcd[0] & 0x60) != 0x60) return iset; // no AVX512
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iset = 9; // 8: AVX512F supported
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return iset;
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}
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// detect if CPU supports the FMA3 instruction set
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bool hasFMA3(void) {
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if (instrset_detect() < 7) return false; // must have AVX
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int abcd[4]; // cpuid results
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cpuid(abcd, 1); // call cpuid function 1
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return ((abcd[2] & (1 << 12)) != 0); // ecx bit 12 indicates FMA3
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}
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// detect if CPU supports the FMA4 instruction set
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bool hasFMA4(void) {
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if (instrset_detect() < 7) return false; // must have AVX
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int abcd[4]; // cpuid results
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cpuid(abcd, 0x80000001); // call cpuid function 0x80000001
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return ((abcd[2] & (1 << 16)) != 0); // ecx bit 16 indicates FMA4
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}
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// detect if CPU supports the XOP instruction set
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bool hasXOP(void) {
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if (instrset_detect() < 7) return false; // must have AVX
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int abcd[4]; // cpuid results
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cpuid(abcd, 0x80000001); // call cpuid function 0x80000001
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return ((abcd[2] & (1 << 11)) != 0); // ecx bit 11 indicates XOP
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}
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